1. Field of the Invention
The present invention relates to a thin film transistor for a liquid crystal display (LCD) device and more particularly, to a thin film transistor having a metal signal line for a liquid crystal display device and a manufacturing method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device includes two substrates that are spaced apart and face each other with a liquid crystal material layer interposed between the two substrates. Each of the substrates includes electrodes that face each other, wherein a voltage applied to each electrode induces an electric field between the electrodes and within the liquid crystal material layer. The intensity and direction of the applied electric field affects alignment of liquid crystal molecules of the liquid crystal material layer. Accordingly, the LCD device displays an image by varying light transmissivity through the liquid crystal material layer in accordance with the arrangement of the liquid crystal molecules.
FIG. 1 is an enlarged perspective view of a liquid crystal display (LCD) device according to the related art. In FIG. 1, an LCD device 11 has upper and lower substrates 5 and 22, which are spaced apart from and facing each other, and a liquid crystal material layer 14 interposed between the upper and lower substrates 5 and 22. The upper substrate 5 includes a black matrix 6, a color filter layer 8, and a transparent common electrode 18 subsequently disposed on an interior surface thereof. The black matrix 6 includes openings having one of three sub-color filters of red (R), green (G), and blue (B).
A gate line 13 and a data line 15 are formed on an interior surface of the lower substrate 22, which is commonly referred to as an array substrate, such that the gate line 13 and the date line 15 cross each other to define a pixel area P. In addition, a thin film transistor T is formed at the crossing of the gate line 13 and the data line 15 and includes a gate electrode, a source electrode, and a drain electrode. A pixel electrode 17 is formed within the pixel area P to correspond to the sub-color filters (R), (G), and (B) and is electrically connected to the thin film transistor T. The pixel electrode 17 is made of a light transparent conductive material, such as indium-tin-oxide (ITO).
A storage capacitor C is connected to the pixel electrode 17. The gate line 13 acts as a first capacitor electrode and a metal layer 30 acts as a second capacitor electrode that is connected to the pixel electrode 17. The metal layer 30 is formed when source and drain electrodes for the thin film transistor T are formed.
A scanning pulse is supplied to the gate electrode of the thin film transistor T along the gate line 13, and a data signal is supplied to the source electrode of the thin film transistor T along the data line 15. Accordingly, light transmission through the liquid crystal material layer 14 is adjusted by controlling electrical and optical properties of the liquid crystal material layer 14. For example, the liquid crystal material layer 14 includes a dielectric anisotropic material having spontaneous polarization properties such that the liquid crystal molecules form a dipole when the electric field is induced. Thus, the liquid crystal molecules of the liquid crystal material layer 14 are controlled by the applied electric field. In addition, optical modulation of the liquid crystal material layer 14 is adjusted according to the arrangement of the liquid crystal molecules. Therefore, images on the LCD device are produced by controlling the light transmittance of the liquid crystal material layer 14 due to optical modulation of the liquid crystal material layer 14.
Detailed description of the pixel area P is explained with reference to FIG. 2, which is an enlarged plan view of an array substrate for an LCD device according to the related art. Gate lines 62 and data lines 76 are formed on a substrate 50 to cross each other, thereby defining pixel areas P.
A thin film transistor T is formed at the crossing of each of the gate and data lines 62 and 76 to function as a switching element. The thin film transistor T includes a gate electrode 60 that is connected to the gate line 62 to receive scanning signals, a source electrode 70 is connected to the data line 76 and receives data signals, and a drain electrode 72 is spaced apart from the source electrode 70. In addition, the thin film transistor T includes an active layer 66 between the gate electrode 13 and the source and drain electrodes 70 and 72, and a transparent pixel electrode 80 is formed in the pixel area P and is connected to the drain electrode 72. The pixel electrode 80 is connected to a metal layer 74 and forms a storage capacitor C.
To prevent signal delay on the gate line 62, a low resistance metal, for example aluminum Al or aluminum alloy AlNd, is used as a gate line 62. Because aluminum is chemically weak, chrome Cr or molybdenum Mo is used as a protection layer. Thus, the gate line 62 is formed as a dual layer.
Because there is a difference in etching ratio for the two layers using the same etchant, it is difficult to pattern the dual layered gate line, which will be explained with reference to FIGS. 3A to 3F.
As shown in FIG. 3A, an aluminum material and a molybdenum material are sequentially deposited on a substrate 50, where switching and pixel areas T and P are defined, thereby forming a first metal layer 52 and a second metal layer 54. A photo-resister layer is deposited on the second metal layer 54 and patterned to form a PR pattern 56.
When the exposed portion of the second metal layer 54 and the first metal layer 52 are etched by an etchant, only metal portions 58a and 58b under the PR pattern 56 remain, as shown in FIG. 3B. When a wet etching process is carried out, overhangs are formed because Mo shows a lower etching rate than Al. This overhang causes, during subsequent formation of an insulation film on the signal layer, deterioration of insulation performance of the insulation film by the formation of voids or cavities on the sides of the layer of Al material underlying it
To solve the overhang problem, a dry etching to etch peripheral portions of the second metal portion 58b and the PR pattern 56 is carried out, and the step caused by the overhang becomes smooth as shown in FIG. 3C.
The PR pattern 56 is then removed to expose a gate electrode 60 of Al/Mo in the switching area T and a gate line 62 near the peripherals of the pixel area P as shown in FIG. 3D. Sequentially, on the gate electrode 60 and the gate line 62 a gate insulating layer 64 is formed. The gate insulating layer 64 may be selected from non-organic materials, for example silicon nitride or silicon oxide.
Next, on the gate insulating layer 64, an amorphous silicon layer and a doped amorphous silicon layer are formed and patterned into an active layer 66 and an ohmic contact layer 68, respectively, as shown in FIG. 3E.
After forming the ohmic contact layer 68, a conducting metal such as aluminum Al, aluminum alloy, tungsten W, molybdenum Mo or chrome Cr is deposited and patterned to form source and drain electrodes 70 and 72 contacting the ohmic contact layer 68 and spaced apart from each other. A data line 76 connected to the source electrode 70 is also formed. At the same time, an island-shaped metal layer 74 for a capacitor is formed over the gate line 62.
Next, as shown in FIG. 3F, a passivation layer 78 is formed entirely on the substrate 50 by coating organic material, for example benzocyclobutene (BCB) and an acrylic resin, or by depositing an inorganic material, for example silicon nitride (SiNx) and silicon oxide (SiO2). The passivation layer 78 is patterned to expose portions of the drain electrode 72 and the island shaped metal layer 74.
Next, a pixel electrode 80 is formed on the passivation layer 78 by depositing a transparent conductive material, for example indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), and patterning the transparent conductive material. The pixel electrode 80 is connected to the drain electrode 72 and the island-shaped metal layer 74 via the exposed portions of the drain electrode 72 and the island shaped metal layer 74, respectively.
An array substrate may be manufactured as explained above, but when forming the gate line and the gate electrode, both wet etching and dry etching should be carried out to overcome the overhang problem. Accordingly, the total manufacturing time increases.